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Author: Admin | 2025-04-28
Array, all bonding pads are accessible. For example, for an 8 x 8 TTC array, heat can be generated at selected cells. See figure 6.The process for creating an RDL on the wafer consists of creating one or more metal layers between insulation layers. The metal layers are etched to form traces that connect the existing chip contact pads to created new pads in desired locations. Depending on the trace routing complexity, there will be multiple layers of metal and insulator stacked upon one another. The new pads can be used for wire bonding connection or act as the base for adding Flip Chip bumps.Figure 9 is a TTC-1002 2X3 array with an RDL that provides for wire bonding either along specific locations on the periphery or down the center of the chip. The RDL is a custom requirement that needs to be discussed in detail with TEA before any implementation can begin.How Hot Is Hot?Calculating power density using empirical data derived from Thermal Test Chips, IC designers and packaging engineers can model the actual performance of a product well in advance of committing a design to silicon or a package to hard tooling. Semiconductor process advancements are merging heretofore incompatible pieces of complex systems onto a single substrate. Gone are the days of isolating the power elements to their own heat sunk packages. Now they reside a few microns away from temperature sensitive structures. Something has to give. Or does it?The use of Thermal Test Chips allows designers to
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