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Author: Admin | 2025-04-28
Logic bricks. In Proceedings of the 44th Annual Design Automation Conference, San Diego, CA, USA, 4–8 June 2007; pp. 344–349. [Google Scholar]Guruswamy, M.; Wong, D.F. Echelon: A multilayer detailed area router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996, 15, 1126–1136. [Google Scholar] [CrossRef]Maziasz, R.L.; Hayes, J.P. Layout optimization of static CMOS functional cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990, 9, 708–719. [Google Scholar] [CrossRef]Martins, R. Closing the Gap Between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance Regressors. Electronics 2024, 13, 4360. [Google Scholar] [CrossRef]Kim, J.; Kang, S.M. An efficient transistor folding algorithm for row-based CMOS layout design. In Proceedings of the 34th Annual Design Automation Conference, Anaheim, CA, USA, 9–13 June 1997; pp. 456–459. [Google Scholar]Basaran, B.; Rutenbar, R.A. An O (n) algorithm for transistor stacking with performance constraints. In Proceedings of the 33rd Annual Design Automation Conference, Las Vegas, NV, USA, 3–7 June 1996; pp. 221–226. [Google Scholar]Mirhoseini, A.; Goldie, A.; Yazgan, M.; Jiang, J.; Songhori, E.; Wang, S.; Lee, Y.J.; Johnson, E.; Pathak, O.; Bae, S.; et al. Chip placement with deep reinforcement learning. arXiv 2020, arXiv:2004.10746. [Google Scholar] Figure 1. The main design process of a standard cell layout. Figure 1. The main design process of a standard cell layout. Figure 2. Placement design process of Q-learning algorithm. Figure 2. Placement design process of Q-learning algorithm. Figure 3. Action operation process of Q-learning algorithm. Figure 3. Action operation process of Q-learning algorithm. Figure 4. The conflict and planning design diagram of routing process. Figure 4. The conflict and planning design diagram of routing process. Figure 5. The schematic diagram of the overall design process for a standard cell layout: (a) the front-end netlist; (b) JSON file for placement; (c) placement canvas; and (d) schematic of key dimensions in the migration strategy. Figure 5. The schematic diagram of the overall design process for a standard cell layout: (a) the front-end netlist; (b) JSON file for placement; (c) placement canvas; and (d) schematic of key dimensions in the migration strategy. Figure 6. The schematic diagram
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