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Author: Admin | 2025-04-28
- Requirements Constraints to drive the synthesis process – Clock Period – IN/OUT delays – Max Area/Power Technology library – Timing view – Power consumption – Area Occupation RTL Gate Level Netlist Synthesis Tech Lib Constraints 15 Synthesis – Analyze design Check the syntax of the HDL files – Checks if the file is compliant with one of the supported HDL files (Verilog/VHDL) Check the synthesizability of the design – Reports if some of the non-synthesizable construct have been used Identify the connectivity of the block – All the ports and their directions are identified 16 Synthesize - Elaborate Identifies all the components inferred in the RTL Map the inferred components to a Generic Library (GTECH) Applies the required optimizzation on the RTL (ex. Clock Gating) 17 Synthesis – Elaborate – an example module simpleadder(ina,inb,out,clk); input [3:0] ina; input [3:0] inb; output [4:0] out; reg [4:0] out; input clk; reg [3:0] internal_a; reg [3:0] internal_b; reg [4:0] internal_res; always @(posedge clk) begin internal_a 18 Synthesis – Linking And Opcond Setup Set the Operating Condition at which the synthesis will take place (process voltage and temperature P.V.T.) Select the target library Links the design to other pre-characterized blocks or hard macros 19 Synthesis – Tech Mapping and Optimization The GTECH components are mapped onto the technology library Logic is minimized Implementation of basic building blocks (e.g. adders) are chosen considering the area/power/timing budget 20 Synthesis – Map & Opt an example Internal_a Out internal_b 21 Timing Design and Delay Test Timing simulation: Critical paths are identified by static (vector-less) timing analysis tools like Primetime (Synopsys). Timing or circuit-level simulation using designer- generated functional vectors verifies the design. Layout optimization: Critical path data are used in placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement. Testing:
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