Comment
Author: Admin | 2025-04-28
Two registered stages of a module.1.2.14. Incomplete sensitivity listSensitive list should contain all inputs. If inputs are missed in the sensitivity list, then the changes of that inputs will not be recognised by simulator. Synthesised logic in most cases may correct for the blocks containing incomplete sensitivity list. But this may cause simulation mismatches between source RTL and synthesised netlist. Generally synthesis tools issue a warning for the “always” block having incomplete sensitivity list. Registers can also be added in the sensitive list.1.2.15. Avoid latch inferenceØ “if-else” statements must be end with ‘else’ statements. Else ‘unintentional latches’ will be realized (at output) due to the missing ‘else’ statement at the end.Ø Same is true for ‘case’ statement. ‘default’ statement must be added.Work Around:Either include all possible combination of inputs or initialise the value before the loop starts.Eg.:if(z) a=b;Above code will infer a latch. Because if z=1, value of ‘a’ is defined. But if z=0 value of ‘a’ is not specified. Hence it is assumed that previous value has to be retained and hence latch is infered.Eg.:module latch_inf_test(a, x, y, t, out);input [2:0] a;input x, y, t;output out; reg out;always @(a or x or y or t)begin case(a) 3’b001:out=x; 3’b010:out=y; 3’b100:out=t;endcaseendendmoduleEg.:module case_latch(dout,sel,a,b,c);input [1:0] sel;input a,b,c;output dout;reg dout;always @(a or b or c or sel)begincase (sel)2'b00 : dout = a;2'b01 : dout = b;2'b10 : dout = c;endcaseendendmodule(Above code and figure are Courtesy of Cadence Manuals)Preventing a Latch by Assigning a Default Value module case_default(dout,sel,a,b,c);input [1:0] sel;input a,b,c;output dout;reg dout;always @(a or
Add Comment