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Author: Admin | 2025-04-28
Synthesis using DC, we will use a set of script files toautomate the placement and route task. All the commands for placement and routeare in the template file 'encounter.tcl'. It includescommands to input the gate-level netlist, floorplan the chip, place the cells, route the cells, andto verify and output the result in GDSII format, which is the most popularformat for IC layouts. The circuit to be placed and routed is specified in thefile 'encounter.conf'. Similar to 'compile_dc.tcl', although you don'tneed to modify 'encounter.conf' for this tutorial,you will need to modify it for the final project. The only place you need to change are the lines # Specify the name of your toplevel moduleset my_toplevel accuThisvariable 'my_toplevel' will be used to deduct variousfile names. So it should be the same as in 'compile_dc.tcl'.Now we are ready to run Encounter. The command line is encounter -init encounter.tclEncounter will run for a while and create substantial amounts of output. Wecan obtain more accurate timing by reading into the file 'timing.rep.5.final'. The outputs of Encounter include a GDSII stream 'final.gds2' and anequivalent Verilog model 'final.v' of the placedcircuit. Similar to 'accu.vh', the top-level modulein 'final.v' still has the name 'accu'and the names of the inputs and the outputs are not changed. From the outsideit is exactly the same circuit as you coded on the RTL level. But on the insideadditional buffers are introduced to reduce interconnect delays and enhanceclocking robustness. A post-P&R simulation can be performed with: xrun gscl45nm.v accu_test.v final.v+access+rThe simulation results should
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