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Author: Admin | 2025-04-28
R and c represents rate and capacity respectively. Table 3 provides the parameter size of r and c for both Ascon operating modes and is also expressed mathematically in Eq. (1). Five registers of 64-bit each are used to model the 320-bit internal state, when realized in hardware. The internal state is accessed starting at the most significant byte (or bit) of \(a_0\) as byte 0 and ends at the least significant byte (or bit) of \(a_4\) as byte 39.$$\begin{aligned} S = Sr \Vert Sc = a0 \Vert a1 \Vert a2 \Vert a3 \Vert a4. \end{aligned}$$ (1) Fig. 1Internal architecture of Ascon AE encryption. (The decryption process is the same except CT is processed to obtain PT)Full size image3.2.1 InitializationThree parameters are concatenated to make the input that can act as the initial state of Ascon. These parameters include the secret key \(S_K\), nonce N, and the pre-defined initialisation vector (IV). To maintain the confidentiality requirement, it is mandatory to refresh N for every encryption process. The initial state goes through 12 rounds of permutation f, and then is XORed with the secret key, i.e., \(S_K\). Equations (2) and (3) represent the complete initialization process.$$\begin{aligned} S&\leftarrow IV \Vert S_K \Vert N \end{aligned}$$ (2) $$\begin{aligned} S&\leftarrow f^a(S) \oplus (0^{320-S_k} \Vert S_K) \end{aligned}$$ (3) 3.2.2 Associated dataProcessing AD is only applicable when there is AD present; otherwise, it can be skipped. Ascon utilizes a chunk-based processing approach for the AD, where each chunk consists of r bits. To ensure that the total
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