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Author: Admin | 2025-04-28
The switching factor, the operating voltage and the clock net capacitance.Internal Power– Internal power is the power dissipated due to the flow of crow-bar current from the power rail to the ground node while both the pull-up and the pull-down network of the clock cells are ON. Internal power directly depends on the clock slew. Worse clock slew allows more crow-bar current and therefore increases the internal power dissipated.Figure 3: Internal PowerImpact of OCVOCVs refer to intra-chip variations in Process, Voltage and Temperature which may result in delay variations of standard cells on silicon. With shrinking technology nodes, the impact of On-Chip Variations has been ever increasing. Clock path to launch and the capture sequential needs to diverge at some point along the clock network. Any clock cells in the clock network before the point of divergence are immune to any OCV variations, while the clock cells after point of divergence are susceptible to intra-chip variations, and may exhibit different delay on silicon. Designers need to model this OCV variation in form of clock skew. Depending upon the clock architecture chosen, the point of divergence may be upstream or downstream along the clock tree.Clock Distribution MethodologiesDesigners may need to choose from among 3 clock distribution methodologies depending on their design specifications:Clock Tree MeshAs the name suggests, clock tree mesh involves a dense mesh of shorted wires to distribute the clock to every corner of the design. It involves many mesh drivers driving a capacitive mesh of wires which are shorted
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