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Author: Admin | 2025-04-28
The serial clock output and serial data output to the ADC.In the serial clock generator process ”p_counter_clock” the serial clock is generated by the division of the board clock. The clock generation is disabled if no conversion is required.The video shows how to implement the serial ADC VHDL code controller on the DE0-nano Altera board.Serial ADC controller VHDL code SimulationIn the simulation windows, the board clock is 50 MHz (20 ns). The Clock division factor is 16 so the generated serial clock will be 3.125 MHz (i.e.320 ns)Figure3 – Serial ADC controller SimulationSerial ADC controller VHDL code implementation on FPGAThe DE0-nano provides 8 LEDs. In order to verify the ADC controller VHDL code, the 8 LEDs of the board are connected to the 8 ADC MSB, so we can use the led to “read” the ADC converted values.The ADC channel is selected using the switch SW 3..1 that will select the serial ADC input channel 0 to 7. The Serial ADC conversion is controlled using SW4 that can enable/disable the ADC conversion.Figure4 – DE0 nano Serial ADC implementation architectureIf you appreciate this post, please help us to share it with your friend.To contact us, please write to: surf.vhdl@gmail.comWe appreciate any of your comments, please post below:
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