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Author: Admin | 2025-04-28
A contacted gate pitch of 45 nanometers, the tightest pitch reported to date by any foundry. It’s worth pointing out that, historically, TSMC relies on a slightly more relaxed CPP for their standard cell implementations. That puts N3B somewhere 45-47 nm for the CPP in real-world implementations.One of the things TSMC introduced with their N3B node is a new self-aligned contact (SAC) scheme. This one surprised us since we thought they would have already introduced it by now. By comparison, Intel introduced SAC at their 22-nanometer process along with their FinFET transistor architecture all the way back in 2011. Samsung also introduced SAC a while back in their 7-nanometer family.One of the many challenges that process engineers face when shrinking transistors is variations due to misalignments. On modern nodes, due to the small contact landing area, the margin for misalignment drops significantly, affecting yield. Beyond contact-to-gate shorts, parasitic capacitance and performance issues as a result also occur. To alleviate the issue, TSMC says that with their N3B and beyond, they have to introduce SAC. SAC – or self-aligned contact – is strictly a yield-improving flow that guards the gate against contact shorts due to the tight pitches in leading-edge process nodes.Under SAC, the gate is guarded against shorts through a dielectric hard mask on top of the gate. It also allows the contact to fully utilize the space adjacent to the spacers. The end product is a process flow that is much more forgiving with respect to process variations. It’s worth noting that the process does have the effect of worsening capacitance due to the proximity of the contact under misalignments.The graph below from TSMC shows how the SAC successfully suppressed the contact-to-gate leakage. Up to 3 nanometers in either direction is shown to have minimal impact on leakage when
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