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Author: Admin | 2025-04-28
Makes sense for your team to put in the extra man-hours to make sure these problem blocks are given a GLS environment with a fast turn time and high simulation speed in order to work through all their expected issues efficiently. ---- ---- ---- ---- ---- ---- ---- 6. Functional Testing, GLS, and internal BFMs Environments that employ internal BFMs use to hijack an internal DUT interface at the boundary of a block to simplify generation of test stimulus. The assumption is that the block will work exactly the same as the BFM in silicon. Leveraging existing tests for use in GLS is critical to making GLS effort cost-effective. Having to rewrite new tests to run without a BFM is extremely expensive. Adding BFMs into your GLS testbenches is tricky however, especially for SDF GLS, but it is possible. System Verilog adds interfaces with clocking blocks which allow set-up and hold application for entire groups of signals very easily, and makes BFMs in GLS to be quite doable. - Leverage Existing Tests and Easier Test Generation Grabbing an existing set of tests is much easier than generating a test suite from scratch. Even if existing tests do not exist, generating stimulus from a BFM is much simpler to create, maintain and debug. WARNING: But you're trusting your BFM. Neither GLS nor RTL simulation will catch if your BSM has subtle errors in it. - Shorter Tests Tests using BFMs are shorter because they can skip the initialization of the logic they replace, and the model simulates faster with a BFM in place of your design block in gates. WARNING: Using BFMs bypasses reset initialization testing of those blocks on your chip -- and often where chip-killer bugs lurk. BFMs make tests quick and faster to create, but they do it
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